r03ds0016ej0100 rev.1.00 2011.09.05 page 1 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 8-bit 2ch d/a converter with buffer R2A20162NS/sa/sp new product description features ? conversion from digital data to analog control data for home-use and industrial equipment. ? signal gain control or automatic adjustment of lcd-tv, pdp-tv or lcd display-monitor. ? blurring correction control or various control of the interchangeable lens of digital camera for self adjustment by combination with microcomputer and eeprom. (substitution of half fixed resistance) block diagram the r2a20162 is an integrated circuit semiconductor of cmos structure with 2 channels of built in d/a converters with output buffer op-amps. it is the electrical characteristic improvement version of the m62342. ? guarantee differential nonlinearity error : +/- 0.7lsb, nonlinearity error : +/- 1.0lsb, ? data transfer format: 10-bit serial data input type by 3 wire ( di, sck, ld ) ? output buffer op-amps: operable over entire voltage range from almost ground to vcc ( 0 to 5v ) ? high output current capacity: +/- 1ma or higher ? very mall size package line-up: son-8 (pin pitch: 0.5mm), tssop-8 (pin pitch 0.65mm) 10-bit shift register 8 7 6 8 channel decoder vcc clkld di gnd ao2 ao1 n.c. power on reset serial data transfer type input can easily be used through a combination of three lines: di, clk, and ld. outputs incorporate buffer op-amps that have a drive capacity of 1 ma or above for both sink source, and can operate over the entire voltage range from almost ground to vcc ( 0 to 5v ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. very small son package is added to lineup. it is suitable for a small mounting and reduces the mounting area. application 8-bit upper segment r-2r 8-bit upper segment r-2r 8-bit latch 8-bit latch 3 2 1 4 5
R2A20162NS/sa/sp new product page 2 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 pin description pin arrangement R2A20162NS (top view) r2a20162sa/sp (top view) 1 2 3 4 8 7 6 5 ao1 ao2 n.c. vcc ld clk di gnd outline: prsp0008de-c [sp] ptsp-0008jc-b [sa] 1 2 3 4 8 7 6 5 ao1 ao2 n.c. vcc ld clk di gnd n.c.: not connected outline: pwsn0008ka-a [ns] gnd terminal gnd 5 power supply terminal vcc 4 not connected n.c. 3 a02 2 8-bit resolution d/a converter output terminals (after power-on, all channels are reset and dac data 00h is output.) ao1 1 load terminal (when high level is input to ld terminal, value in 10-bit shift register is loaded into decoder and 8-bit latch.) ld 8 serial clock input terminal (input signal from di terminal is input to 10-bit shift register at rise of serial clock.) clk 7 serial data input terminal. (input serial data with a 10-bit data length.) di 6 function pin name pin no . n.c.: not connected
R2A20162NS/sa/sp new product page 3 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 tstg topr k theta pd i ao vo vin vcc symbol ta>25deg ta=85deg continuous conditions mw/deg 6.75(ns) / 5.0(sa) / 6.8(sp) thermal derating factor ma -2.0 to +2.0 mw 270(ns) / 200(sa) / 272(sp) power dissipation v -0.3 to vcc+0.3 <6.5 output voltage buffer amplifier output current deg -40 to +125 storage temperature deg -30 to +85 operating temperature v -0.3 to vcc+0.3 <6.5 input voltage v -0.3 to +6.5 supply voltage unit ratings item absolute maximum ratings ( vcc= +5v +/-10%, gnd=0v, ta= -30 to +85deg unless otherwise noted) electrical characteristics *1 : when power supply is turned on, internal circuit is initia lized by power on reset circuit. but, if re-powered on quickly, initialize is not operate. so, k eep the time period of re-powered on (t por ). vcc internal reset signal t por tr vcc < 0.1v (equivalent to tr vcc ) vcc por resetting period gnd gnd v vcc ? 0.8vcc vcc < 4.0v v 1.9 1.5 ? vcc=0 to 2.7v vcc por operating voltage of internal resetting *1 s ? ? 100 vcc=0 to 2.7v tr vcc supply voltage rise-up time *1 ms ? ? 1 vcc < 0.1v t por time period of re-power on (power supply off ? on) *1 ma 2.5 0.7 0 clk = 1mhz operation, i ao =0a, data: 6ah (at maximum current) ma 1.0 ? -1.0 upper side saturation voltage = 0.3v lower side saturation voltage = 0.2v i ao buffer amplifier output drive range vcc=5.12v (20mv/ lsb), without load (i ao = 0a) i ao = +/-500a i ao = +/-100a 4.0v < vcc vin= 0 to vcc sda = scl = gnd, i ao =0a test conditions ro co s full s zero s l s dl v ao v ih v il i ilk icc vcc symbol lsb 2.0 ? -2.0 zero code error ohm ? 5.0 ? buffer amplifier output impedance vcc-0.2 ? 0.2 v vcc-0.1 ? 0.1 buffer amplifier output voltage range lsb 1.0 ? -1.0 nonlinearity a 10 ? -10 input leak current v 0.2vcc ? 0 input low voltage v vcc ? 0.5vcc input high voltage lsb 0.7 ? -0.7 differential nonlinearity lsb 2.0 ? -2.0 full scale error f 0.1 ? ? output capacitate load ma 1.6 0.5 0 supply current v 5.5 5.0 2.7 supply voltage max. typ. min. unit limits item resetting period (ta= +25deg unless otherwise noted)
R2A20162NS/sa/sp new product page 4 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 ac characteristics clk t cr t cf t ckh t ckl t dch t chd t chl t ldh t ldc t ldd di ld d/a output (note) timing chart above is a schematic repres entation of the timing of each signal type. clk signal input is high or low regardless, ld signal high input is enabled. ( vcc = +5v +/-10deg, gnd = 0v, ta = -30 to +85deg unless otherwise noted ) t ldd t ldh t ldc t chl t chd t dch t cf t cr t ckl t ckh f clk symbol ns -- 40 load high pulse width ns -- 40 clock low pulse width ns -- 40 clock high pulse width ns 200 -- clock rise time ns -- 40 load setup time ta=25deg, c l <100pf, v ao : 0.5 ?? 4.5v, the time until the output becomes the final value of 1/2 lsb. test conditions s 150 -- d/a output settling time ns 200 -- clock fall time ns --5 data setup time ns -- 30 data hold time ns -- 40 load hold time mhz 10 1.0 - clock frequency max. typ. min. unit limits item timing chart
R2A20162NS/sa/sp new product page 5 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 digital data format last lsb d5 d6 d9d8d7 d4d3d2d1d0 vcc/256 x 255 11111110 1 : 0 0 0 0 d2 1 : 0 0 0 0 d3 1 : 0 0 0 0 d4 1 : 1 1 0 0 d1 vcc 111 1 : ::: : vcc/256 x 4 000 1 vcc/256 x 3 000 0 vcc/256 x 2 000 1 vcc/256 x 1 000 0 dac output d7d6d5 d0 first msb dac data channel select data channel select data don?t care 1 1 don?t care 1 0 ao2 selected 0 1 ao1 selected 0 0 channel selection d9 d8 dac data data timing chart ( model ) di ld d/a output d2 d7 d8 d9 clk d6 d5 d1 d0 whether clk input is ?h? or ?l?, high level input of ld signal is recognized.
R2A20162NS/sa/sp new product page 6 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 ? supply voltage terminal (vcc) is also used for d/a converter upper reference voltage setting. if ripple or spike is input this terminal, accuracy of d/a converter is down, so, when use this device, please connect capacitor among vcc to gnd for stable d/a conversion. ? this ic?s output amplifier has an advantage to capacit ive load, so, it?s no problem at device action when connect capacitor ( 0.1 f max ) among output to gnd for every noise elimination. precaution for use application example 8 7 6 5 analog output terminals + 10f mcu 5v R2A20162NS / sa / sp ld clk di gnd 4 vcc 3 n.c. 2 ao2 1 ao1 package dimensions pwsn0008ka-a [ns] ordering information embossed taping/3,000 pcs. sa rtsp0008jc-b tssop-8 r2a20162sa embossed taping/2,500 pcs. sp prsp0008de-c sop-8 r2a20162sp embossed taping/5,000 pcs. ns pwsn0008ka-a son-8 R2A20162NS packing/quantity package type no. package code package name order part no.
R2A20162NS/sa/sp new product page 7 of 7 r03ds0016ej0100 rev.1.00 2011.09.05 prsp0008de-c [sp] ptsp0008jc-b [sa]
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